1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same.
2. Related Art
A conventional method of manufacturing a semiconductor device including a MISFET will be described below with reference to FIGS. 13 and 14.
First, a gate dielectric film 4 of silicon oxide (SiO2) is formed on a silicon monocrystal substrate 2 (FIG. 13). Subsequently, a polycrystalline silicon layer is formed on the gate dielectric film 4. Then, phosphorus or arsenic is doped into the polycrystalline silicon layer in a region where an n-channel MOSFET is to be formed, thereby forming an n-type polycrystalline silicon layer 9. At this time, regions other than the region where an n-channel MOSFET is formed are covered by, e.g., a photoresist pattern (not shown).
After the aforementioned resist pattern is removed, another resist pattern (not shown) of, e.g., a photoresist, is formed, the resist pattern having an opening in a region where a p-channel MOSFET is to be formed. Then, boron is doped into the polycrystalline silicon layer in the region where a p-channel MOSFET is to be formed using the resist pattern as a mask, thereby forming a p-type polycrystalline silicon layer 12. Subsequently, the resist pattern is removed.
Thereafter, a resist pattern 14 serving as an etching mask is formed on the polycrystalline silicon layers 9 and 12, the resist pattern 14 having openings at regions other than the regions where gate electrodes are to be formed. A photoresist layer formed by using a photolithography technique is used to form the resist pattern 14.
Next, the silicon monocrystal substrate 2 is carried into a reactive ion etching (RIE) apparatus so as to perform the dry etching of the polycrystalline silicon layers 9 and 12. Generally, a halogen type etching gas, such as hydrogen bromide (HBr) gas, chlorine (Cl2) gas, etc., is used to perform the dry etching (JP Laid-Open Pub. No. 2003-37163). When the etching of the polycrystalline silicon layers 9 and 12 at the bottom of the openings of the resist pattern 14 is started, thin-film removing (etching) is performed from the surface of the polycrystalline silicon layers 9 and 12 in the thickness direction thereof. As a result, the surface of the gate dielectric film 4 is exposed, and the remaining portions of the polycrystalline silicon layers 9 and 12 become gate electrodes 10 and 13, respectively.
Ideally, at this time the etching on the entire surface of the gate dielectric film 4 is stopped. However, since the gate dielectric film 4 is very thin, and a halogen type etching gas cannot secure sufficient etching selectivity with respect to the gate dielectric film 4, it is likely that part of the gate dielectric film 4 is overetched to the degree that an opening is made therethrough.
In order to prevent this, generally, the etching of the polycrystalline silicon layers 9 and 12 is monitored using, e.g., an interference type layer-thickness monitor, and the etching is suspended before reaching the gate dielectric film 4, e.g., when the thickness of the polycrystalline layers 9 and 12 becomes 200 Å to 300 Å. Then, a second etching is performed by using an etching gas having a sufficient etching selectivity with respect to the gate dielectric film 4, such as O2-added HBr gas. The second etching is continued until the gate dielectric film 4 is exposed. During the second etching, the light emission intensity of the silicon reaction product in the polycrystalline silicon layers 9 and 12 is monitored, and the termination of the second etching is decided when the light emission intensity is decreased.
After the etching is completed, the gate electrodes 10 and 13, to which impurities are doped to make them either n-type or p-type, are formed.
Generally, the etching rate of the n-type polycrystalline silicon layer 9 differs from that of the p-type polycrystalline silicon layer 12. Accordingly, in most of the cases, the gate dielectric film 4 in the region where the n-type polycrystalline silicon layer 9 is formed is exposed earlier than the gate dielectric film 9 in the region where the p-type polycrystalline silicon layer 12 is formed during the first and second etching steps. As a result, the gate dielectric film 4 could be overetched, exposing the silicon monocrystal substrate 2 around the gate electrodes 10 formed of the n-type polycrystalline silicon, as shown in FIG. 15. In addition, the gate electrodes 13 formed of the p-type polycrystalline silicon may be insufficiently etched and have a lip portion at the lower end thereof, as shown in FIG. 15. Thus, the gate length of the n-type gate electrode 10 at the interface with the gate dielectric film 4 may differ from that of the p-type gate electrode 13.
Generally, etching rates may vary at different places on a surface of a polycrystalline silicon layer since plasma density distribution in a reactive ion etching apparatus may become uneven, or active species may be unevenly inserted into a polycrystalline silicon layer that becomes a gate electrode. Accordingly, the etching rate at the edge portions of the polycrystalline silicon substrate may be faster than the etching rate at the central portion thereof, resulting in that the gate dielectric film 4 might be overetched, exposing its base layer around the gate electrodes formed at the edge portions, and the gate electrodes formed at the central area may have a lip portion.
Further, the etching rate may vary depending on the density of the formed pattern. The etching rate of a gate electrode 20 shown in FIG. 16, which is spatially isolated, may be faster than the etching rate of gate electrodes 21, which are densely formed. Thus, the gate dielectric film 4 may be excessively etched around the gate electrode 20, or the shape of gate electrode 20 may be affected negatively.